The present invention relates to a driver circuit using a transistor and, more particularly, to a driver circuit capable of a large-amplitude output at a high speed.
The implementation of a wide-band, high-output amplifier capable of DC high-speed operation and large-amplitude driving has been expected as semiconductor integrated circuits for optical modulator driver, laser driver, and large-amplitude logical interface output. Also, the implementation of a high-speed, high-output amplifier capable of high-frequency operation and large-amplitude driving has been expected as a power amplifier for a wireless system. The present invention relates to a circuit arrangement which implements such amplifier.
FIG. 15 shows the arrangement of the output stage of a conventional driver circuit using a field effect transistor (to be referred to as an FET hereinafter) with a source-grounded circuit. Reference symbol GND denotes ground; Vdd, a positive power supply voltage; Vin, an input signal voltage; Vout, an output signal voltage; T1, an FET; and R1, a resistor.
Reference symbol Vds denotes a voltage of the drain of the FET to the source; and Vdsmax and Vdsmin, maximum and minimum design values of Vds. Letting Vdsbd be the positive breakdown voltage of the drain of the FET to the source, Vdsmax<Vdsbd must be established. Letting Vgd be the voltage of the gate to the drain, Vgdmax and Vgdmin be the maximum and minimum design values of Vgd, and Vgdbd be the negative breakdown voltage of the gate of the FET to the drain, Vgdmin>Vgdbd must be established.
In the prior art, a change Vdsmax−Vdsmin in Vds of one FET is extracted as an output amplitude on the output stage of the driver circuit in the source-grounded circuit. That is, Vout having an amplitude larger than Vdsmax−Vdsmin cannot be output. This also applies to an emitter-grounded circuit using a bipolar transistor.
According to Japanese Patent Laid-Open No. 3-73917 (FIG. 5 of this reference), the power supply bias is properly set. When a gate-source voltage Vgs is set to a high level Vgsmax for both two series-connected FETs on the output stage, a drain-source voltage Vds can be set to a low level Vdsmin. When Vgs is set to a low level Vgsmin, Vds can be set to a high level Vdsmax. When an input signal is sufficiently low in speed, the total voltage applied to the two series-connected transistors can be equally divided by the two transistors, and a signal having an amplitude twice an amplitude outputtable by one transistor can be output.
FIG. 16 shows the arrangement of the output stage of a driver circuit disclosed in Japanese Patent Laid-Open No. 3-73917. In this arrangement, transistors T1 and T2 are series-connected between a power supply voltage Vdd and ground GND. An input signal voltage Vin is simultaneously applied to the gate electrodes of the transistors (FETs) T1 and T2.
In the technique disclosed in Japanese Patent Laid-Open No. 3-73917, the driving timings of the gate electrodes of the two FETs basically coincide with each other. If a high-speed signal is input, the voltage balance between the two FETs is lost, and the voltage readily exceeds the breakdown voltage of the transistor.
[Reason That Voltage Readily Exceeds Breakdown Voltage]
Letting τ be the delay time of an inverter formed from one transistor, the rise and fall times unique to the inverter are given by 2τ. Assume that a high-speed signal corresponding to the rise/fall time 2τ is input. When the two series-connected transistors T1 and T2 change from OFF to ON, a gate voltage Vg1 of the lower transistor T1 changes from low level (Vg1off) to high level (Vg1on) (FIG. 17A). Vds of the transistor T1 changes from Vdsmax to Vdsmin after the delay time τ of the transistor T1 (FIG. 17B).
This means that a source potential Vs2 (FIG. 17B) of the transistor T2 changes from high level Vs2max=Vdsmax to Vs2min=Vdsmin at a time τ after a gate voltage Vg2 (FIG. 17C) of the upper transistor T2 changes from high level to low level.
Owing to the delay of Vs2 from Vg2, a large negative undershoot occurs in a gate-source voltage Vgs2 of the transistor T2, as shown in FIG. 17D. The time when the gate-source voltage of the transistor T2 changes from OFF to ON delays by almost 2τ from the time of the transistor T1.
As a result, the voltage division balance in drain-source voltage between the transistors T1 and T2 is greatly lost in changing from OFF to ON. As shown in FIGS. 17E and 17F, large undershoots occur in a drain-source voltage Vds2 and gate-drain voltage Vgd2 of the transistor T2. The voltage readily exceeds the breakdown voltage.
Note that an undershoot means a spike which occurs in a direction opposite to a change at the beginning of the change. An overshoot means a spike which occurs in the same direction as a change at the end of the change.